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? e93512a78-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage v dd ?.5 to +7.0 v input voltage v i ?.5 to v dd +0.5 v output voltage v o ?.5 to v dd +0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd +4.5 to +5.5 v (standard +5.0) operating temperature topr ?0 to +75 ? description the cxd1186c is a cd-rom decoder lsi. features corresponds to cd-rom, cd-i and cd-rom xa formats. real time error correction. (erasure correction using c2 pointer from cd player.) double speed playback. connection to standard sram up to 64 k bytes, as buffer memory, possible. applications cd-rom driver structure silicon gate cmos ic cd-rom decoder cxd1186cq cxd1186cr 80 pin qfp (plastic) 80 pin lqfp (plastic) cxd1186cq/cr
? cxd1186cq/cr block diagram data bclk c2po lrck cdp i/f control reg descramble sync control +2 hclk xtl2 xtl1 hdb0-7, p hmds adrq xaac ha0, 1 xtc hint s/p word center decode timing gen driive address counter latch registers ecc control galois field reg reg syndrome cpu i/f priority resolver dma sequencer cpu dma db0? a0? int host dma host address counter host i/f regs dma fifo adp i/f host i/f regs v dd gnd bdb0?, p ba0?5 xrst xwr xrd xcs hdbp xhwr xhrd xhcs xdrq xhac xmwr xmoe
? cxd1186cq/cr pin configuration cxd1186cq 1 2 3 4 5 6 7 8 9 10 11 14 15 12 13 16 17 20 21 18 19 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 22 64 63 62 61 60 59 58 57 56 55 54 51 50 53 52 49 48 45 44 47 46 42 41 43 int gnd a0 a1 a2 a3 hmds ha0 ha1 xhcs hint gnd xhrd xhwr hdb0 hdb1 hdb2 hdb3 hdb4 hdb5 hdb6 hdb7 gnd hdbp ba8 ba7 ba6 ba5 ba4 ba3 ba2 v dd ba1 ba0 xaac adrq xtc xhac hdrq 79 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 xrst hclk gnd xtl1 xtl2 bdbp bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 gnd bdb0 xmwr xmoe ba15 ba14 ba13 ba12 ba11 ba10 gnd ba9 lrck data bclk c2po db0 db1 db2 db3 v dd db4 db5 db6 db7 xcs xrd xwr cxd1186cr 1 2 3 4 5 6 7 8 9 10 11 14 15 12 13 16 17 20 18 19 25 26 27 28 21 22 23 24 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 51 50 53 52 49 48 45 44 47 46 42 41 43 a0 a1 a2 a3 hmds ha0 ha1 xhcs hint gnd xhrd xhwr hdb0 hdb1 hdb2 hdb3 hdb4 hdb5 hdb6 hdb7 gnd ba9 ba8 ba7 ba6 ba5 ba4 ba3 ba1 v dd ba1 fa0 xaac adrq xtc 79 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 xhac hdrq xrst hdrp gnd xtl1 xtl2 bdbp bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 gnd bdb0 xmwr xmoe ba15 ba14 ba13 ba12 ba11 ba10 bclk c2po db0 db1 64 63 62 61 gnd hclk lrck data db2 db3 v dd db4 db5 db6 db7 xcs xrd xwr int gnd
? cxd1186cq/cr pin description pin no. symbol i/o description cxd1186cq cxd1186cr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 int gnd a0 a1 a2 a3 hmds ha0 ha1 xhcs hint gnd xhrd xhwr hdb0 hdb1 hdb2 hdb3 hdb4 hdb5 hdb6 hdb7 gnd hdbp xrst hdrq xhac xtc adrq xaac ba0 ba1 v dd ba2 ba3 ba4 ba5 ba8 ba7 o i i i i i i i i o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i o i i i o o o o o o o o o interrupt request signal to cpu gnd pin cpu address signal cpu address signal cpu address signal cpu address signal host mode select signal host address signal host address signal chip select negative logic signal from host interrupt request negative logic signal to host gnd pin data read strobe signal from host or to scsi control ic data write strobe signal from host or to scsi control ic host data bus host data bus host data bus host data bus host data bus host data bus host data bus host data bus gnd pin error flag, host data bus reset negative logic signal data request positive logic signal to host. or dma acknowledge negative logic signal to scsi control ic dma acknowledge negative logic signal from host. or data request positive logic signal from scsi control ic terminal count negative logic signal dma request positive logic signal from adp dma acknowledge negative logic signal to adp buffer memory address buffer memory address power (+5 v) supply pin buffer memory address buffer memory address buffer memory address buffer memory address buffer memory address buffer memory address
? cxd1186cq/cr pin no. symbol i/o description cxd1186cq cxd1186cr 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 ba8 ba9 gnd ba10 ba11 ba12 ba13 ba14 ba15 xmoe xmwr bdb0 gnd bdb1 bdb2 bdb3 bdb4 bdb5 bdb6 bdb7 bdbp xtl2 xtl1 gnd hclk lrck data bclk c2po db0 db1 db2 db3 v dd db4 db5 db6 db7 xcs xrd xwr o o o o o o o o o o i/o i/o i/o i/o i/o i/o i/o i/o i/o o i o i i i i i/o i/o i/o i/o i/o i/o i/o i/o i i i buffer memory address buffer memory address gnd pin buffer memory address buffer memory address buffer memory address buffer memory address buffer memory address buffer memory address buffer memory output enable negative logic signal buffer memory write negative logic signal buffer memory data bus gnd pin buffer memory data bus buffer memory data bus buffer memory data bus buffer memory data bus buffer memory data bus buffer memory data bus buffer memory data bus buffer memory pointer data bus crystal oscillation circuit output pin crystal oscillation circuit input pin gnd pin 1/2 frequency divided clock signal of xtl1 lr clock from cd player serial data from cd player bit clock from cd player c2 pointer from cd player cpu data bus cpu data bus cpu data bus cpu data bus power (+5 v) supply pin cpu data bus cpu data bus cpu data bus cpu data bus chip select negative logic signal from cpu cpu strobe negative logic signal to read out this ic internal register cpu strobe negative logic signal to write in this ic internal register
? cxd1186cq/cr electrical characteristics dc characteristics (v dd =5 v10 %, v ss =0 v, topr=?0 to +75 ?) item input voltage h level l level ttl schmitt hysterisis input current of pull up input input current of pull down input output voltage h level l level open drain output l level oscillation cell h level input voltage l level logic threshold value feedback resistance output voltage h level l level symbol v ih1 v il1 (v t +)?v t ? i il i ih v oh1 v ol1 v ol2 v ih v il lv th r fb v oh v ol conditions v il =0 v v ih =v dd i oh =? ma i ol =4 ma i ol =4 ma v in =v ss or v dd i oh =? ma i ol =1 ma min. typ. max. unit 2.2 v 0.8 v 0.2 0.4 v ?0 ?00 ?40 a 40 100 240 a v dd ?.8 v 0.4 v 0.4 v 0.7 v dd v 0.3 v dd v v dd /2 v 250 k 1 m 2.5 m v dd /2 v v dd /2 v input pin with pull up resistance : xhcs, ha0, ha1, xtc input pin with pull down resistance : c2po, hmds, adrq ttl schmitt input pin : xrst open drain output pin : hint two-way data bus always pulled up. oscillation cell input : xtl1 output : xtl2 i/o capacitance v dd =v i =0 v, f=1 mhz item input pin output pin i/o pin symbol c in c out c i/o min. typ. max. 9 11 11 unit pf pf pf
? cxd1186cq/cr ac characteristics (ta=?0 to +75 ?, v dd =5 v10 %, output load=50 pf, f 24.576 mhz) 1. cpu interface (1) read (2) write a0 to 3 xcs xrd db0 to 7 t hra t rrl t sar t drd t frd item address setup time (vs. xcs & xrd ) address hold time (vs. xcs & xrd - ) data delay time (vs. xcs & xrd ) data float time (vs. xcs & xrd - ) low level xrd pulse width symbol t sar t hra t drd t frd t rrl min. 30 20 0 100 typ. max. 60 10 unit n n n n n a0 to 3 xcs xwr db0 to 7 t hwd t hwa t sdw t wwl t saw item address setup time (vs. xcs & xwr ) address hold time (vs. xcs & xwr - ) data setup time (vs. xcs & xwr - ) data hold time (vs. xcs & xwr - ) low level xwr pulse width symbol t saw t hwa t sdw t hwd t wwl min. 30 20 40 10 50 typ. max. unit n n n n n where & in the chart indicates logical multiplication.
? cxd1186cq/cr 2. memory interface (1) read (2) write ba0 to 15 t rrl t sao t hoa t hod t sdo xmoe bdb0 to 7, p item address setup time (vs. xmoe ) address hold time (vs. xmoe - ) data setup time (vs. xmoe - ) data hold time (vs. xmoe - ) low level xmoe pulse width symbol t sao t hoa t sdo t hod t rrl min. tw?2 tw? 45 0 2 ?tw typ. max. 2?w+16 unit n n n n n ba0 to 15 t wwl t saw t hwa t fwd t dwd xmwr bdb0 to 7, p item address setup time (vs. xmwr ) address hold time (vs. xmwr - ) data delay time (vs. xmwr ) data float time (vs. xmwr - ) low level xmwr pulse width symbol t saw t hwa t dwd t fwd t wwl min. tw?9 tw? 10 2 ?tw typ. max. 0 unit n n n n n where tw=1/f. usually, when f=16.9344 mhz, use a ram with access time within 120 ns.
? cxd1186cq/cr 3. host interface (1) read (2) write ha0 to 1 t hra t rrl t frd t drd t sar xhcs xhrd hdb0 to 7, p item address setup time (vs. xhcs & xhrd ) address hold time (vs. xhcs & xhrd - ) data delay time (vs. xhcs & xhrd ) data float time (vs. xhcs & xhrd - ) low level xhrd pulse width symbol t sar t hra t drd t frd t rrl min. 30 20 0 100 typ. max. 60 10 unit n n n n n ha0 to 1 t saw t wwl t sdw t hwd t hwa xhcs xhwr hdb0 to 7, p item address setup time (vs. xhcs & xhwr ) address hold time (vs. xhcs & xhwr - ) data setup time (vs. xhcs & xhwr - ) data hold time (vs. xhcs & xhwr - ) low level xhwr pulse width symbol t saw t hwa t sdw t hwd t wwl min. 30 20 40 10 50 typ. max. unit n n n n n
?0 cxd1186cq/cr 4. host dma cycle (80 type bus) (1) read (2) write hdrq t dar2 t hra t rrl t sar t dar1 t drd t frd xhac xhrd hdb0 to 7, p item hdrq fall time (vs. xhac ) hdrq rise time (vs. xhac - ) xhac setup time (vs. xhrd ) xhac hold time (vs. xhrd - ) low level xhrd pulse width data delay time (vs. xhrd ) data float time (vs. xhrd - ) symbol t dar1 t dar2 t sar t hra t rrl t drd t frd min. 5 0 100 0 typ. max. 35 48 60 10 unit n n n n n n n hdrq t saw t wwl t hwa t hwd t sdw t dar1 t dar2 xhac xhwr hdb0 to 7, p item hdrq fall time (vs. xhac ) hdrq rise time (vs. xhac - ) xhac setup time (vs. xhwr ) xhac hold time (vs. xhwr - ) low level xhwr pulse width data setup time (vs. xhwr - ) data hold time (vs. xhwr - ) symbol t dar1 t dar2 t saw t hwa t wwl t sdw t hwd min. 5 0 50 40 10 typ. max. 35 48 unit n n n n n n n
?1 cxd1186cq/cr 5. host dma cycle (scsi bus) (1) read (2) write sdrq t dda t dar t rrl t dra t hrd t drd xsac xhrd hdb0 to 7, p item xsac fall time (vs. sdrq - ) xsac delay time (vs. xhrd ) xsac delay time (vs. xhrd - ) low level xhrd pulse width data delay time (vs. xhrd ) data hold time (vs. xhrd - ) symbol t dda t dar t dra t rrl t drd t hrd min. 0 t+59 0 typ. max. tw tw 90 unit n n n n n n sdrq t dda t daw t wwl t dwa t fwd t sdw xsac xhwr hdb0 to 7, p item xsac fall time (vs. sdrq - ) xhwr delay time (vs. xsac ) xsac delay time (vs. xhwr - ) low level xhwr pulse width data setup time (vs. xhwr ) data float time (vs. xhwr ) symbol t dda t daw t dwa t wwl t sdw t fwd min. t t+24 27 typ. max. tw tw tw unit n n n n n n where t in the chart indicates : tw for 3 cycle mode 2 ?tw for 4 cycle mode 3 ?tw for 5 cycle mode here tw=1/f
?2 cxd1186cq/cr 6. adpcm dma cycle where t in the chart indicates : tw for 3 cycle mode 2 ?tw for 4 cycle mode 3 ?tw for 5 cycle mode here tw=1/f 7. xtl1 and xtl2 pins (1) for self oscillation (topr=?0 to +75 ?, v dd =5.0 v10 %) (2) when a pulse is input to xtl1 (topr=?0 to +75 ?, v dd =5.0 v10 %) adrq t wwl t dwa t daw t dda t sdw t fwd xaac xhwr hdb0 to 7, p item xaac fall time (vs. adrq - ) xhwr delay time (vs. xaac ) xaac delay time (vs. xhwr - ) low level xhwr pulse width data setup time (vs. xhwr ) data float time (vs. xhwr ) symbol t dda t daw t dwa t wwl t sdw t fwd min. t t+24 27 typ. max. tw tw tw unit n n n n n n t w t r t f t whx t wlx t ilx v ihx v ihx x0.9 v ihx x0.1 v dd/2 xtl1 item ??level pulse width ??level pulse width pulse period input ??level input ??level rise time, fall time symbol t whx t wlx t w v ihx v ilx t r , t f min. 15 15 40.7 v dd ?.0 typ. max. 0.8 15 unit ns ns ns v v ns item oscillation frequency symbol f max min. 16.9344 typ. max. 24.576 unit mhz
?3 cxd1186cq/cr description of function 1. pin description below is a description of pins by function. 1.1 cd player interface (4 pins) (1) data (input) serial data from circ lsi (digital signal processing lsi for cd) (2) bclk (input) bit clock. clock for data strobe. (3) lrck (input) lr clock. indicates l ch and r ch of data input. (4) c2po (positive logic input) c2 pointer signal from circ. indicates an error is included in the data input. interface mode with the cd player is controlled at drvif register. 1.2 buffer memory interface (27 pins) (1) xmwr (memory write, negative logic output) data write strobe signal of the buffer memory. (2) xmoe (memory output enable, negative logic output) data read strobe signal of the buffer memory. (3) ba0 to 15 (buffer memory address, output) address signal of the buffer memory. (4) bdb0 to 7 (buffer data bus, i/o) data bus signal of the buffer memory. (5) bdbp (buffer data bus, i/o) buffer memory data bus signal for error pointer. 1.3 cpu interface (16 pins) (1) xwr (cpu write, negative logic input) write strobe signal of the cpu register. (2) xrd (cpu read, negative logic input) read out strobe signal of the cpu register. (3) xcs (cpu chip select, negative logic input) chip select negative logic signal from the cpu. (4) a0 to 3 (cpu address, input) address signal for the cpu selection of the ic internal register. (5) db0 to 7 (cpu data bus, i/o) cpu data bus signal. (6) int (cpu interrupt, output) interrupt request output to the cpu. this pin polarity is controlled at the config register. 1.4 host interface (19 pins) (1) hmds (host mode select, input) signal for the host mode selection. this pin is pulled down inside the ic by means of a resistor at a standard 50 k . ??or open : connected to intel 80 type host bus. ? : connected to scsi controller ic. (2) hdrq/xsac (host data request/scsi acknowledge, output) when hmds is at ?? dma data request positive logic signal to host. when hmds is at ?? dma acknowledge negative logic signal to scsi control ic.
?4 cxd1186cq/cr (3) xhac/sdrq (host dma acknowledge/scsi data request, input) when hmds is at ?? dma acknowledge negative logic signal from host. when hmds is at ?? dma data request positive logic signal from scsi control ic. (4) xhwr (host write, negative logic i/o) when hmds is at ??and admaen (dmactl register, bit4) also at ?? data write strobe input from host. when hmds is at ??and admaen at ?? data write strobe output to scsi control ic. when admaen is at ?? data write strobe output to audio processor (adp). (5) xhrd (host read, negative logic i/o) when hmds is at ??and admaen also at ?? data read strobe input from host. when hmds is at ??and admaen at ?? data read strobe output to scsi control ic. when admaen is at ?? data read strobe output to adp. (6) xhcs (host chip select, negative logic input) this pin is pulled up inside the ic by means of a resistor at a standard 50 k . when hmds is at ?? chip select input from host. when hmds is at ?? this signal is not used. either fix to ??or keep open. (7) ha0 and 1 (host address, input) these pins are pulled up inside the ic by means of a resistor at a standard 50 k . when hmds is at ?? address input from the host. when hmds is at ?? these signals are not used. either fix to ??or keep open. (8) hdb0 to 7 (host data bus, i/o) host data bus signal. (9) hdbp (host data bus, i/o) host data bus signal for error pointer. (10) hint (host interrupt, output) this pin is an open drain output. when hmds is at ?? interrupt request negative logic output to host. when hmds is at ?? this signal is not used. (11) xtc (terminal count, negative logic output) this is pulled up inside the ic by means of a resistor at a standard 50 k . when hmds is at ?? data transfer complete instruction negative logic input from the host. when hmds is at ?? this signal is not used. either fix to ??or keep open. 1.5 audio processor (adp) interface (2 pins) (1) adrq (audio processor dma request, positive logic input) this pin is pulled down inside the ic by means of a resistor at a standard 50 k . dma data request signal to adp. when not connected to adp and cxd1186q, either fix to ??or keep open. (2) xaac (audio processor dma acknowledge, negative logic output) dma acknowledge signal from adp. 1.6 others (4 pins) (1) xtl1 (crystal1, input) (2) xtl2 (crystal2, output) crystal oscillator connecting pin for master clock oscillation. (3) hclk (halfclock, output) half frequency divided clock of the master clock. (4) xrst (reset, negative logic input) chip reset signal. pins bdb0 to 7, bdbp, db0 to 7, hdb0 to 7 and hdbp are pulled up inside the ic by means of a resistor at a standard 25 k .
?5 cxd1186cq/cr 2. register function this ic is controlled from the cpu by means of 19 registers for each of write and read, respectively. 2.1 write register 2.1.1 drive interface (drvif) register bit0 : digin (digital in) ? ; when digital in (see fig. 2.1.1) is connected, this bit is set to ?? ? ; when connected to circ lsi, this bit is set to ?? bits 2 to 5 are effective only when digin is at ?? bit1 : lsb1st (lsb first) ? ; when data is connected to circ lsi output through lsb first, this bit is set to ?? ? ; when data is connected to circ lsi output through msb first, this bit is set to ?? bits2 and 3 : bckmd 0, 1 (bclk mode 0, 1) these bits are set according to the number of bclk clocks output during one word by circ lsi. bckmd 1 bckmd 0 ? ? 16bclks/word ? ? 24bclks/word ? ? 32bclks/word moreover, when there are 24 or 32 clocks within 1 word, the 16 bits of data before lrck edge, become effective. bit4 : bckred (bclk rising edge) ? ; data is strobed with bclk rise. ? ; data is strobed with bclk fall. bit5 : lchlow (lch low) ? ; when lrck is at ?? it is determined to be l ch data. ? ; when lrck is at ?? it is determined to be l ch data. * 1. when digin=?? we automatically have lsbist=bckmd1=?? bckred=lchlow=?? bit6 : dblspd (double speed) ? ; at double speed pb, this bit is set to ?? ? ; at normal speed pb, this bit is set to ?? bit7 : c2plist (c2po lower-byte 1st) ? ; when 2 bytes of data are input to c2po, the lower-byte and the upper-byte are input in the order. ? ; when 2 bytes of data are input to c2po, the upper-byte and the lower-byte are input in the order. table 2.1.1 indicates the setting value of bits 0 to 7 when sony-made circ lsi is connected. fig. 2.1.1 (1) to (4) indicates the input timing chart. here, the upper byte means the upper 8 bits including msb from circ lsi, lower byte indicates the lower 8 bits including lsb from circ lsi. changes in value for the respective bits in this register have to be executed in the decoder disable condition.
?6 cxd1186cq/cr lrck bclk data rch validity flag rch lsb rch ?msb l0 rv r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 lv 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 fig. 2.1.1 (1) digital in timing chart (c2po don? care, no need for connection) lrck bclk data c2po rch lsb lch msb lch ?lsb c2 pointer for upper byte c2 pointer for lower byte r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 1 2 3 4 5 6 7 8 9 101112131415161718192021222324 fig. 2.1.1 (2) cdl30, 35 series, timing chart
?7 cxd1186cq/cr lrck bclk data c2po rch lsb lch msb lch lsb c2 pointer for upper byte c2 pointer for lower byte r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 12345 6789101112131415161718192021222324 fig. 2.1.1 (3) cxd2500q, 48 bit slot mode timing chart 1234567891011121314151617181920212223242526272829303132 lrck bclk data c2po lch msb rch lsb rch msb l14 l15 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 c2 pointer for upper byte c2 pointer for lower byte fig. 2.1.1 (4) cxd2500q, 64 bit slot mode timing chart
?8 cxd1186cq/cr table 2.1.1 drvif register setting value (note 1) * at normal speed pb set to ?? at double speed pb set to ?? (note 2) 2.1.2 decoder control (decctl) register bits0 to 2 : decmdsl2, 1, 0 (decoder mode select 2, 1, 0) decmdsl2 1 0 ? ? ? decoder disable ? ? ? monitor only mode ? ? ? write only mode ? ? ? real time correction mode ? ? ? repeat correction mode ? ? ? cd-da mode bit3 : autodist (auto distinction) ? ; error correction performed according to the mode byte and form bit read from drive. ? ; error correction is performed according to the following modesel and formsel bits. bit4 : formsel (form select) bit5 : modesel (mode select) when autodist is at ??the sector is corrected as the following mode or form. modesel formsel ? ? mode1 ? ? mode2, form1 ? ? mode2, form2 bit6 : eccstr (ecc strategy) ? ; error correction is performed with consideration to respective data error flag. l ; error correction is performed without consideration to respective data error flag. when an 8 bit/word ram is connected, turn this bit to ?? bit7 : endladr (enable dladr) ? ; when this bit is set to ?? dladr is enabled. when, either write only mode, real time correction, or cd-da mode is being executed, the decoder stops the buffer write as dadrc and dladr turn equal. ? ; when this bit is set to ?? dladr is disabled. during the execution of write only mode or real time correction, even if dadrc and dladr turn equal, the decoder does not stop buffer write. (see paragraph 4 for details) sony-made circ lsi cdl30 series cdl35 series cdl40 series (48 bit slot mode) cdl40 series (64 bit slot mode) drv if register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 l * lllhll l * lhlhll l * hlhxhl timing chart fig. 2.1.1 (2) fig. 2.1.1 (3) fig. 2.1.1 (4) cdl30 series cdl35 series cdl40 series cxd1125q/qz, cxd1130q/qz, cxd1135q/qz, cxd1241q/qz, cxd1245q, cxd1246q/qz, cxd1247q/qz/r and others. cxd1165q, cxd1167q/qz/r and others. cxd2500q/qz and others.
?9 cxd1186cq/cr 2.1.3 dma control (dmactl) register bit0 : hsrc (host source) ? ; data is transferred from the host to the buffer memory. ? ; data is transferred from the buffer memory to the host. bit1 : hdmaen (host dma enable) ? ; dma of the host port is enabled. ? ; dma of the host port is prohibited. bit2 : enxtc (enable xtc) ? ; dma completion of the host port through xtc pin input is enabled. ? ; dma completion of the host port through xtc pin input is disabled. bit3 : enhxfrc (enable xhfrc) ? ; dma completion of the host port through hxfrc is enabled. ? ; dma completion of the host port through hxfrc is disabled. bit4 : admaen (adp dma enable) ? ; dma of the audio processor port is enabled. ? ; dma of the audio processor port is prohibited. also, prohibits turning hdmaen and admaen simultaneously to ?? bit5 : csrc (cpu source) ? ; data is transferred from the cpu to the buffer memory. ? ; data is transferred from the buffer memory to the cpu. bit6 : cdmaen (cpu dma enable) ? ; dma of the cpu port is enable. ? ; dma of the cpu port is prohibited. bit7 : reserved unused, keep set to ?? 2.1.4 configuration (config) register bit0 : reserved unused, keep set to ?? bits1 and 2 : sdmacyc1, 0 (scsi dma cycle) dma transfer between this ic, scsi control ic and adpcm processor is executed in the following cycle. sdmacyc1 0 ? ? 3 cycle. ? ? 4 cycle. ? ? 5 cycle. bit3 : sbsctl (scsi bus control) setting this bit to ??forces xhwr, xhrd, hdb0 to 7 and hdbp into high impedance condition. bit4 : cintposi (cpu interrupt positive) ? ; int pin turns to high active. ? ; int pin turns to low active. bit5 : 9 bitram ? ; when a 9 bit/word ram is connected, this bit is turned to ?? ? ; when a 8 bit/word ram is connected, this bit is turned to ?? bits6 and 7 : reserved unused, keep set to ??
?0 cxd1186cq/cr 2.1.5 interrupt mask (intmsk) register turning the respective bits of the register to ??enables interrupt request from this ic to the cpu by means of the corresponding interrupt status. (that is, when interrupt status is turned on, int pin is activated) the value of the respective bits in this register does not affect the corresponding interrupt status. bit0 : decint (decoder interrupt) when the decoder is executing one of the respective modes, write only, monitor, or real time correction, if sync mark is detected or introduced, decint status is turned on. however, when sync detection window is open, if sync interval is less than 2352 bytes, decint status is not turned on. also, when decoder repeat correction mode is being executed, everytime one correction is completed decint status is turned on. bit1 : hdmacmp (host dma complete) when dma of the host port is completed through hxfrc or xtc pins, hdmacmp status is turned on. bit2 : drvovrn (drive over run) when endladr bit (bit7) of decctl register is set to ?? and the decoder has executed write only, real time correction mode or cd-da mode, as dadrc and dladr become equal, drvovrn status is turned on. however, in cd-da mode, even when endladr bit is turned to ?? drvovrn status is turned on. bit3 : hstcmnd (host command) as the host writes a command in the command register, hstcmnd status is turned on. bit4 : hcrisd (host chip reset issued) by having the host write ??in chprst bit (bit7) of the control register, this ic is reset and hcrisd status is turned on. bit5 : rsltempt (result empty) when the host reads the result register, and the result register becomes empty, rsltempt status turns on. bit6 : dectout (decoder timeout) after setting the decoder to either, monitor only, write only or real time correction modes, if, even after the time of three sectors (normal speed pb 40.6 ms) passes, sync is not detected, then dectout status is turned on. 2.1.6 clear interrupt status (intclr) register when any of the respective bits of this register is set to ?? the corresponding interrupt status is cleared. after the interrupt status clearance, the bit automatically turns to ?? accordingly there is no need for the cpu to set to ??again. bit0 : decint (decoder interrupt) bit1 : hdmacmp (host dma complete) bit2 : drvovrn (drive over run) bit3 : hstcmnd (host command) bit4 : hcrisd (host chip reset issued) bit5 : rsltempt (result empty) bit6 : dectout (decoder timeout) 2.1.7 drive ?last ?address ?low (dladr-l) register
?1 cxd1186cq/cr 2.1.8 drive ?last ?address ?high (dladr-h) register when the decoder is executing either of write only, real time correction mode or cd-da mode, cpu sets the last address that writes into the buffer, data from the drive. when endladr bit of decctl register is set to ??and the decoder is executing the above modes, if data from the drive is written into the buffer at the address specified from dladr, all writing into the buffer is prohibited after that. 2.1.9 drive ?address ?low (dadrc-l) counter 2.1.10 drive ?address ?counter high (dadrc-h) this counter keeps the address that writes data from the drive into the buffer. when drive data is written into the buffer, dadrc contents are output form ba0 to 15. for every byte written in the buffer, dadrc is incremented. before the decoder executes either write only, real time correction mode or cd-da mode, cpu sets the buffer write head address to dadrc. this counter can also be used as the dma address of the cpu port. during dma execution of the cpu port, dadrc contents are output from ba0 to 15, dadrc is incremented at every byte of dma execution. cpu can read or set dadrc contents at any time. do not alter dadrc contents during either write only, real time correction or cd-da mode and the dma execution of cpu port. 2.1.11 host ?address ?low (hadrc-l) counter 2.1.12 host ?address ?high (hadrc-h) counter this counter keeps the address that writes data from the host into the buffer or reads from the buffer. during execution of the host port dma, hadrc contents are output from ba0 to 15. the counter is incremented at every dma of the host port. before execution of the host port dma, cpu sets the dma head address to hadrc. cpu can read or set hadrc contents at any time, do no alter hadrc contents during host port dma execution. 2.1.13 host ?transfer ?low (hxfrc-1) counter 2.1.14 host ?transfer ?high (hxfrc-h) counter this counter indicates the number of host port dma transfers. it is decremented at every host port dma. when enhxfrc bit (bit3) of dmactl register is set to ??and hxfrc value turns to 0, the host port dma is disabled. at that time it is possible to send an interrupt request from this ic to the cpu. cpu can read and set hxfrc contents at any time. do not alter hxfrc contents during host port dma execution. 2.1.15 chip control (chpctl) register bit0 : cpubwpo (cpu buffer write pointer) sets the pointer value for cpu port dma (buffer write). bit1 : chprst (chip reset) setting this bit to ??initializes the interior of this ic. after the initialization of the interior of this ic is completed, this bit automatically turns to ?? accordingly it is not necessary to set the cpu to ?? bit2 : swopn (sync window open) ? ; setting this bit to ??opens the window to allow for sync mark detection. sync protection circuit inside this ic is disabled. ? ; setting this bit to ??controls the window through the sync protection circuit inside the ic. bit3 : rpstart (repeat correction start) setting the decoder to repeat correction mode and this bit to ??starts the sector error correction. as correction starts, this bit automatically turns to ?? accordingly it is not necessary to set the cpu to ?? bits4 to 7 : do not fail to set to ?? if set to ??ic operation is not guaranteed.
?2 cxd1186cq/cr 2.1.16 cpu buffer write data (cpubwdt) register with the cpu port dma (buffer write), data is written into this register. when cdmaen of dmactl register=csrc=?? write into this register is subject to the request of cpu port dma (buffer wire). see paragraph 6 for details. 2.1.17 host interface control (hifctl) register when hmds is at ?? this register controls the hardware of the host interface. bit0 : hint #1 (host interrupt #1) this bit value becomes the value of hintsts #1 (bit0) from status register on the host side. bit1 : hint #2 (host interrupt #2) this bit value becomes the value of hintsts #2 (bit1) from status register on the host side. bit2 : hint #3 (host interrupt #3) this bit value becomes the value of hintsts #3 (bit2) from status register on the host side. (note) once ??is written, until bits 0 to 2 are cleared from the host or the chip is reset, keep at ?? it is not possible to access the register from the cpu and turn bits 0 to 2 from ??to ?? accordingly, to set any of these bits, it is not necessary to take into consideration the value of other bits. when hintsts bit #1 to 3 from hifsts register that corresponds to the above bits are at ?? it is prohibited to write ??in the above bits. therefore, before the cpu writes ??in the above bits hifsts register should be read, and confirmation made that corresponding hintsts bits #1 to 3 are at ?? bits3 to 5 : reserved unused. keep set to ?? if set to ??the ic operation is not guaranteed. bit6 : clrrslt (clear result) when this bit is set to ?? the result register is cleared. when these register? clearance is completed, this bit automatically turns to ?? therefore, there is no need for the cpu to set back to ?? bit7 : clrbusy (clear, busy) when this bit is set to ?? busysts bit of hintsts register is cleared. when these register? clearance is complete, this bit turns automatically turns to ?? therefore, there is no need for the cpu to reset to l. 2.1.18 drive result (drvrslt) register this register is utilized to transfer the command execution result to the host, when hmds=?? this register is composed of a 10 bytes fifo. for details see 4.2.1. 2.1.19 register address (regadr) register bits0 to 6 : do not fail to set to ?? if set to ??the ic operation is not guaranteed. bit7 : regadr0 (register address0) this bit is used for the register address expansion. 2.2 read out register 2.2.1 current minute address low (cmadr-l) register 2.2.2 current minute address high (cmadr-h) register indicates the buffer memory address where the current sector (after correction is completed) minute bytes are written.
?3 cxd1186cq/cr 2.2.3 header (hdr) register a three bytes register that indicates the current sector header byte. by reading address 0h successively 4 times the cpu can know the header byte value of the current sector, starting from the minute byte. 2.2.4 sub header (shdr) register a three bytes register that indicates the current sector sub header byte. by reading address 1h successively 4 times, the cpu can know the sub header byte value of the current sector, starting from the file byte. 2.2.5 header flag (hdrflg) register indicates the header and sub header error pointer value. 2.2.6 interrupt status (intsts) register the value of the respective bits in this register indicates the condition of the corresponding interrupt status. the bit value of intmsk register does not affect the above mentioned bits. bit0 : decint (decoder interrupt) bit1 : hdmacmp (host dma complete) bit2 : drvovrn (drive over run) bit3 : hstcmnd (host command) bit4 : hcrisd (host chip reset issued) bit5 : rsltempt (result empty) bit6 : dectout (decoder timeout) 2.2.7 decoder status (decsts) register bit0 : nosync indicates that sync mark could not be detected and that sync was inserted. bit1 : shrtsct (short sector) indicates the sync mark interval was within 2352 bytes. this sector does not execute ecc and edc. bit2 : eccok (ecc ok) indicates there are no more errors from the header of the sector where error correction was completed up to p parity byte. (in form2, this bit turns to don? care.) bit3 : edcok indicates edc check showed there were no errors. bit4 : cordone (correction done) indicates that sector contains bytes that were error corrected. bit5 : corinh (correction inhibit) indicates there was an error flag at mode (and from) bytes when autodist bit of decoder register was turned to ?? this sector does not execute ecc and edc. bit6 : erinblk (erasure in block) turns to ??when c2 pointer from circ lsi stood in 1 byte or more of all the bytes, with the exception of current sector sync byte. bit7 : edcall0 (edc all zero) this bit turns to ??when there are no error flags in any of edc parity bytes of current sector, and the value is at 00h.
?4 cxd1186cq/cr 2.2.8 mode form (mdfm) register this register is effective only during the execution of real time correction mode or repeated correction mode. bit0 : cform (correction form) bit1 : cmode (correction mode) these bits indicate whether this ic identified mode and form in that sector and executed error correction. cmode cform ? ? mode1 ? ? mode2, form1 ? ? mode2, form2 bits2 to 4 : rmode0, 1, 2 (raw mode) rmode1, 0 : indicates the lower 2 bits value of raw mode byte. rmode2 : indicate the logical sum of the upper 6 bits and pointer in raw mode byte. 2.2.9 dma status (dmasts) register bit0 : cbfwrdy (cpu buffer write ready) this bit turns to ??when data written from cpu into cpubwdt register is written in the buffer memory. as cpu writes the next data into cpubwdt register, it turns to ??until that data is written into the buffer memory. also, when csrs is set to ??and cdmaen to ??(dmactl register), this bit turns to ?? cpu confirms this bit is at ??and writes in the data into cpubwdt register. bit1 : cbfrrdy (cpu buffer read ready) when data read from buffer memory is kept ready in cpubrdt register, this bit turns to ?? when cpu reads cpubrdt register out it turns to ?? cpu confirms this bit is at ??and reads out data from cpubrdt register. bit2 : cbfrdpo (cpu buffer read pointer) indicates the value of the pointer bit read from the buffer memory. bit7 : regadr (register address) this bit indicates the value of bit7 from register address register. 2.2.10 dadrc-l counter 2.2.11 dadrc-h counter 2.2.12 hadrc-l counter 2.2.13 hadrc-h counter 2.2.14 hxfrc-l counter 2.2.15 hxfrc-h counter 2.2.16 cpu buffer read data (cpubrdt) register cpu port dma (buffer read) data is read out from this register. when cdmaen of dmactl register is at ??and csrc at ?? the read out of this register is set for the dma (buffer read) request of the next cpu port. 2.2.17 host parameter (hstprm) register when hmds is at ?? this register is used to know the command parameter from the host. this register is composed of a 10 bytes fifo.
?5 cxd1186cq/cr 2.2.18 host command (hstcmd) register when hmds is at ?? this register is used to know the command from the host. 2.2.19 host interface status (hifsfs) register when hmds is at ?? this register is used to know the host interface condition. bit0 : hintsts #1 (host interrupt status #1) this bit turns to ??as cpu writes ??into hint #1 (hifctl register bit0). it turns to ??when the host writes ??into clrint #1 (control register bit0). this bit is used as interrupt status monitor to the host. bit1 : hintsts #2 (host interrupt status #2) this bit turns to ??as cpu writes ??into hint #2 (hifctl register bit1). it turns to ??when the host writes ??into clrint #2 (control register bit1). this bit is used as interrupt status monitor to the host. bit2 : hintsts #3 (host interrupt status #3) this bit turns to ??as cpu writes ??into hint #3 (hifctl register bit2). it turns to ??when the host writes ??into clrint #3 (control register bit2). this bit is used as interrupt status monitor to the host. bit3 : prmrrdy (parameter, read ready) this bit at ??indicates that hstprm register is not empty, so that parameter data can be read out from the cpu. when this bit is at ?? hstprm register is empty and parameter data cannot be read out from the cpu. bit4 : prmfull (parameter full) this bit at ??indicates hstpram register is full. bit5 : rslwrdy (result write ready) this bit at ??indicates that drvrslt register is not full, so that the cpu can write result data. when this bit is at ??drvrslt register is full and the cpu can not write result data. bit6 : rslempt (result empty) this bit at ??indicates drvrslt register is empty. bit7 : busysts (busy status) this bit has the same value as that of busysts (bit7) of the status register on the host side. this bit turns to ??as the host writes a command in the command register. it turns to ?? as the cpu sets clrbusy bit of hifctl register.
?6 cxd1186cq/cr ***** write register ***** drive interface (drvif) decoder control (decctl) digin decmdsl0 lsb1st decmdsl1 bckmd0 decmdsl2 bckmd1 autodist bcked formsel lchlow modesel dblspd eccstr c2pl1st endladr dma control (dmactl) configuration (config) hsrc reserved ? hdmaen sdmacyc0 enxtc sdmacyc1 enhxfrc sbsctl admaen cintposi csrc 9bitram cdmaen reserved ? corwrids reserved ? interrupt mask (intmsk) clear interrupt status (intclr) decint detint hdmacmp hdmacmp drvovrn drvovrn hstcmd hstcmd hcrisd hcrisd rsltempt rsltempt dectout dectout chip control (chpctl) host interface control (hifctl) cpubwpo hint#1 chprst hint#2 swopn hint#2 rpstart ? ? ? ? ? ? clrfifo ? clrbusy 76543210 76543210 76543210 76543210 76543210 76543210 76543210 76543210
?7 cxd1186cq/cr register address (regadr) ? ? ? ? ? ? ? regadr ***** read register ***** header flag interrupt status dttype decint submode hdmacmp channel drvovrn file hstcmd mode hcrisd block rsltempt second dectout minute decoder status modeform nosync cform shrtsct cmode eccok rmode0 edcok rmode1 cordone rmode2 corinh erinblk edcallo 76543210 76543210 76543210 76543210 76543210 drive ?last ?address ?low drive ?last ?address ?high drive ?address ?counter ?low drive ?address ?counter ?high host ?transfer ?counter ?low host ?transfer ?counter ?high host ?address ?counter ?low host ?address ?counter ?high cpu buffer write register drive status register register address register
?8 cxd1186cq/cr dma status host interface status cbfwrrdy hint#1 cbfrdrdy hint#2 cbfrdpo hint#3 prmrrdy prmfull rslwrdy rslempt regadr busysts header register sub header register current ?minute ?address ?low current ?minute ?address ?high drive ?last ?address ?low drive ?last ?address ?high drive ?address ?counter ?low drive ?address ?counter ?high host ?transfer ?counter ?low host ?transfer ?counter ?high host ?address ?counter ?low host ?address ?counter ?high cpu ?address ?counter ?low cpu ?address ?counter ?high cpu buffer read register host command register host parameter register 76543210 76543210
?9 cxd1186cq/cr cxd1186q register address 0 1 2 3 4 5 6 7 8 9 a b c d e f write read register-address register-address lhlh drvif config hdr decctl shdr dmactl hdrflg intmsk modeform intclr decsts dladr-l intsts dladr-h dmasts dadrc-l dadrc-h hxfrc-l hxfrc-h test2 hadrc-l test1 hadrc-h test0 cpubwdt hifctl cpubrdt hstcmd chpctl drvrslt cmadr-l hstprm regadr cmadr-h hifsts 3. decoder operation here after, the block containing functions 1 and 2 is called decoder. 1 interface with circ lsi the data stream from circ lsi is taken in, while sync detection, descramble and data write to the buffer are executed. 2 error correction executes error correction of the sector written in the buffer. 3.1 decoder operation mode the decoder features 4 operation modes set by means of decmdsel0 to 2 bits of decctl register. decmdsl2 1 0 ? ? ? decoder disable ? ? ? monitor only mode ? ? ? write only mode ? ? ? real time correction mode ? ? ? repeat correction mode ? ? ? cd-da mode (1) decoder disable decoder operation is disabled. (2) monitor only mode data from the drive is not written in the buffer. raw data from the drive is written in the header, sub header and hdrflg registers. (3) write only mode set to this mode, first sync pattern detection is performed. as sync pattern is detected, write from that sector into the buffer starts from minute byte. the buffer memory address of this minute byte, is the value set to dadrc though the cpu before setting the decoder mode. sectors after that, and the sync pattern too, are written into the buffer. this buffer write continues until either decoder is disabled or when endladr is at ?? dladr value becomes equal to that of dadrc.
?0 cxd1186cq/cr (4) real time correction mode buffer write works the same as write only mode. at the same time, error correction of the sectors already written in the buffer is executed in real time. (when this mode is set and while the first sector is being written in the buffer, as long as a whole sector is not yet stored in the buffer, correction is not executed.) (5) repeat correction mode data from the drive is not written in the buffer. error correction of sectors already written in the buffer can be executed repeatedly. this way, errors that could not be corrected during real time correction mode, can now be corrected. (6) cd-da mode to write cd-da (digital audio) disc data into the buffer, this mode is set. as this mode is set, write into the buffer is executed from the lower byte of lch. this buffer write continues until either decoder is disabled, or when endladr is at ?? dladr value becomes equal to that of dadrc. 3.2 dadrc (drive address counter) dadrc is the counter that holds the address when data from the drive is written into the buffer. when data from the drive is written into the buffer, the contents are output from ba0 to 15 as buffer memory address. cpu can set or read dadrc contents. cpu sets the buffer write head address in dadrc before the setting of decoder write only mode, real time correction mode and cd-da mode. 3.3 dladr (drive last address) dladr is the register that indicates in bytes the value of dadrc that stops the drive data buffer write during the execution of write only mode, real time correction mode and cd-da mode. when endladr bit of decctl register is at ??and the above modes are being executed, if dadrc value becomes equal to dladr, it stops the buffer write data from the drive. then, drvovrn status is on. when sync interrupt applies and drvovrn bit is at ?? have cpu disable the decoder. when endladr bit is at ?? even if dadrc value becomes equal to dladr, buffer write of the data from the drive is not stopped and drvovrn status does not turn on. through the usage of dladr, buffer overran of the drive can be prevented. when a value is set to dladr, make sure to set the upper byte first and the lower byte next in the order. (even in case only the value of one of bytes is to be changed, set both bytes in the mentioned order. if this is not performed, ic operation can not be guaranteed.) the dladr upper byte is first set then the lower byte is set and until data from the drive is written in the buffer, the above function is disabled. dladr setting should be made carefully. 3.4 error correction (1) mode and form discrimination mode and form discrimination in the sector that performs error correction is executed in bits autodist, formsel and modesel of decctl register, as indicated in fig. 3.1.
?1 cxd1186cq/cr (2) ecc strategy can be chosen through eccstr bit of decctl register. at ?? error correction is performed taking into consideration error flags from respective data. at ?? error correction is performed without taking into consideration error flags from respective data. for systems using 8 bit word ram, turn eccstr to ?? when double speed pb is executed (dblspd of drvif register is at ??, transfer speed to the host slows down. data transfer speed to the host when xtl1 frequency is set to 16.9344 mhz is shown below, moreover, this data transfer speed is the value obtained when data buffer write from the drive, error correction and data transfer to the host are executed at the same time. from the above table, it appears that during double speed pb, data transfer speed to the host decreases. during double speed pb, read data speed from the drive is at 352.8 kb/s. data transfer speed to the host at 0.7 mb/s is quite faster than this read speed. actually, transfer speed to the host does not decrease and as read data speed from the drive doubles, transfer speed to the host also approximately doubles. 3.5 cpu control of the ic during real time correction cpu control of the ic during the ic execution of real time correction mode is shown in fig. 3.2. 3.6 cpu control of the ic during repeat correction cpu control of the ic during the ic execution of repeat correction mode is shown in fig. 3.3. normal pb speed double pb speed eccstr l h l h data transfer speed 2.1 mb/s 0.7 mb/s
?2 cxd1186cq/cr start auto dist = ??? raw mode error n n n n n n y y y y y y y raw mode 1 ? mode 1 correction mode set = ??? set corinh = ? raw sub mode error? form 1 form 1 correction form set = ? form 2 correction fig. 3.1 mode form discrimination method
?3 cxd1186cq/cr start set dadrc dlstadr set decctl : (real time correction mode) rd intsts dec interrupt status ? clear dec interrupt rd hdr, hdrflg header error in byte target sector ? rd decsts shrtcst y y y y y y y n n n n seek necessary decoder disable n n error in current sector transfer to host ? rd cmadr repeated correction repeated correction retry n n n y y drvovrn ? decoder disable transfer to host all sectors decode ? decoder disable end fig. 3.2 cpu control of the ic during real time correction
?4 cxd1186cq/cr repeat correction set decctl set chpctl rd intsts dec interrupt status clear dec interrupt rd hdr, hdrflg error in header byte? target sector rd decsts error in current sector? rd cmadr decoder disable transfer to host all sectors decode decode remaining sector end one more correction? y y y y y n n n n n repeat correction mode (rpstart) fig. 3.3 cpu control of the ic during repeated correction
?5 cxd1186cq/cr 4. host interface 4.1 host i/f mode this ic can be connected to the following, as the host interface. 1 scsi controller ic (cxd1180, cxd1185 and others) 2 intel 80 type host bus this mode is set by means of hmds pin, as shown below. when intel 80 type host bus is connected, hmds input is at ?? otherwise, hmds pin is set to open. when scsi control ic is connected, hmds input is at ?? 4.2 connected to intel 80 type host bus when this ic is connected to intel 80 type host bus either ??is input to pin hmds or it is left open. this connection is shown an fig. 4.1. 4.2.1 command/status transfer between the host and the cpu. (1) register the host can access each of the 4 write and read registers. using pins xhcs, ha0, ha1, xhrd and xhwr, it reads and writes their registers. dma transfer is also possible with rddata and wrdata registers despite xhcs, ha0 and ha1 values. their registers are selected by means of xhac, xhrd, xhwr and dma transfers performed with the host. parameter register and result register are 10 bytes fifo registers. ??input to xhac and xhcs is prohibited at the same time. * write register command register (address 0) the host writes commands in this register. as the host writes in this register, interrupt request is applied from this ic to the cpu. bit assignment and function attribution is performed by means of a control program. parameter register (address 1) to execute commands, the host writes into this register command parameters. this is a 10 bytes fifo register. write data (wrdata) register (address 2) this register serves to write data from the host into the buffer memory. data can be written into either i/o mode or dma mode. this register is composed of a 2 9 bits fifo. control register (address 3) this register is for the direct control of the hardware in this ic by the host. bits0 to 2 : intclr #1 to 3 (clear interrupt #1 to 3) setting these bits to ??will clear the corresponding interrupt status, after the clearance of interrupt status in these bits, they automatically go back to ?? bits3 to 5 : enint #1 to 3 (enable interrupt #1 to 3) setting these bits to ??will enable the corresponding interrupt status. the host can read the respective bits value from the status register. when the corresponding interrupt status is at ?? it is prohibited to write ??to these bits, accordingly, before the host sets these bits to ?? the status register should be read out and interrupt status confirmed. bit6 : clrprm (clear fifo) setting this bit to ??clears the parameter register, after these registers are cleared, this bit automatically goes back to ?? bit7 : chprst (chip reset) setting this bit to ??initializes the inside of this ic. as the inside of this ic initialization is completed, this bit automatically return to ?? setting this bit to ??enables interrupt request to the cpu.
?6 cxd1186cq/cr * read out register status register (address 0) the host uses this register to read this ic status. bits0 to 2 : intsts #1 to 3 (interrupt status #1 to 3) the value of the respective bits is the same as that of the bits corresponding to hifctl register of the sub cpu. when interrupt corresponding to the respective bits is enabled, they turn to ? and interrupt request to the host is output. bits3 to 5 : enintst #1 to 3 (enable interrupt status #1 to 3) the value of the respective bits is the same as that of the bits corresponding to control register. bit6 : dreqsts (data request status) indicates this ic is in buffer memory data transfer request condition versus the host. this bit has the same value as that of pin hdrq. in i/o mode, when buffer memory data transfer is executed, access wrdata register or rddata register after the host confirms this bit is at ?? bit7 : busysts (busy status) this bit turns to ??as the host writes a command into the command register. it turns to ??as the sub cpu sets clrbusy bit of hifclt register. result register (address 1) the host reads the results after the command execution from this register. this is a 10 bytes fifo. read data (rddata) register (address 2) this register is for the host to read data from the buffer memory. data can be read in i/o mode or dma mode. it is composed of a 2 9 bits fifo. fifo status register (address 3) this register is for the host to read the status of parameter or result register. bit0 : prmwrdy (parameter write ready) when this bit is at ??it indicates that parameter register is not full, and that the host can write parameter data. bit1 : prmeempt (parameter empty) this bit at ??indicates parameter register is empty. bit2 : rslrrdy (result read ready) this bit at ??indicates that result register is not empty, and that the host can read result data. bit3 : rslfull (result full) this bit at ??indicates result register is full. bit4 to 7 : reserved unused. address 0 1 2 3 write command parameter write data control read status result read data fifo status
?7 cxd1186cq/cr control status clrint#1 intsts#1 clrint#2 intsts#2 clrint#3 intsts#3 enint#1 enintsts#1 enint#2 enintsts#2 enint#3 enintsts#3 clrfifo dreqsts chprst busysts fifo status prmwrdy prmempt rslrrdy rslfull 76543210 76543210 76543210
?8 cxd1186cq/cr (2) host and cpu controlling order an example of the host and cpu controlling order is shown in fig. 4.2.1. in this case the host gets to know interrupt status by polling status register, interrupt request can also be enabled. 4.2.2 data transfer between the host and the buffer memory. data transfer between the host and the buffer memory is executed through this ic. this ic incorporates a 2 9 bits fifo (wrdata, rddata registers) to speed up data transfer. (1) data transfer in dma mode data transfer between the host and fifo inside this ic, is performed through handshake utilizing hdrq/xsac and xhac/sdrq. hdrq/xsac becomes the hdrq data transfer request signal from this ic to the host while xhac/sdrq becomes the corresponding acknowledge signal xhac. 1 data transfer from the host to the buffer memory (hsrc at ?? when hdmaen is at ??while fifo in not full and xhac is at ?? this ic activates hdrq. as acknowledge signal xhac comes back from the host, hdrq is inactivated. with the rising edge of xhac, data is written into fifo. data written into fifo is written in the buffer memory address in the order prescribed by hadrc. 2 data transfer from the buffer memory to the host (hsrc at ?? when hdmaen is at ?? buffer read data from the address prescribed by hadrc is written into the fifo. as data is written into fifo, if xhac is at ?? this ic activates hdrq. as the acknowledge xhac comes back from the host, hdrq is inactivated. during the period when xhac is at ?? this ic outputs the fifo data to hdb0 to 7. (2) data transfer in i/o mode the host can transfer data to and from the buffer memory, by writing or reading registers wrdata and rddata. in this case the control of cxd1186q by the cpu is the same as during dma transfer mode. fig. 4.2.2 indicates the host control flow when data transfer is performed in i/o mode between the host and the buffer memory. (3) data transfer completion the 3 following methods are for data transfer completion. hxfrc is used. xtc pin is used. hdmaen bit is set to ?? 1 when hxfrc is used: when hxfrc is used for data transfer completion, perform the following before the cpu starts data transfer. set the number of data transfer bytes at hxfrc. set the data transfer direction (hsrc bit) to ??or ??and enhxfrc=hdmaen to ?? this starts data transfer. hxfrc is decremented every time data is written into fifo. when hxfrc turns to 0, writing of data into fifo after that is not performed. then, when all the fifo data is transferred to the buffer memory or the host, hdmacmp status (dmasts register) sets on. when hdmacmp bit of intmsk register is set to ?? this ic outputs interrupt request (int output) to the cpu. 2 when xtc pin is used when xtc pin is used for data transfer completion, perform the following before the cpu starts data transfer. set the data transfer direction (hsrc bit) to ??or ??and enxtc=hdmaen to ?? this starts data transfer.
?9 cxd1186cq/cr during the host final dma byte transfer, turn pin and xhac, xhwr, xhrd to ?? this way, data transfer to the host is no more performed. (hdrq is not output to the host.) when hsrc is at ??and xtc turns to ?? after xhac becomes inactive, this ic turns to hdmacmp status. in this case, 1 byte of unnecessary data from the buffer memory may already be written in the fifo. then, care should be exercised as the last address of hadrc transfer +2 is indicated. when hsrc is at ?? the ic turns to hdmacmp status, when the writing into the buffer memory of data written into the fifo as xtc at ?? is completed. in either case, as hdmacmp status sets on, and hdmacmp bit of intmsk register is set to ?? this ic output interrupt request (int output) to the cpu. both enxtc and enhxfrc bits of dmactl register, can simultaneously be set to ?? (note) in either 1 or 2 case, after hdmacmp sets on, before starting up data transfer again, turn bit 1 of intclr register to ??and clear hdmacmp status. 3 when hdmaen bit is set to ? when hdmaen bit is set to ??during data transfer with the host, data transfer is stopped. then, data transfer between this ic and the host or the buffer memory may be stopped half-way. the value of hadrc and hxfrc after that is not guaranteed. also, in this case, hdmacmp status does not set on. (4) cpu control of the ic cpu control of the ic when data transfer is performed between the host and the buffer memory is illustrated as follows. (in this example execute data transfer completion using hxfrc) 1 the number of transfer bytes is set to hxfrc. 2 hadrc is set at the dma head address. 3 set the data transfer direction to ??or ??and hdmean and enhxfrc bits of dmactl register to ?? 4 as the transfer of the specified number of bytes is completed, hdmacmp bit of dmasts register turns to ?? (then, this ic can output an interrupt request to the cpu) 5 also, hxfrc is at 0000h, while hadrc value stands as the value next to that of the buffer memory address transferred last. 4.3 when connected to scsi control ic when this ic is connected to scsi control ic, hmds pin is set to ?? 4.3.1 connection method to scsi control ic an example for the connection of this ic to an scsi control ic where cpu bus and dma bus are not separated (ex. cxd1180aq) is shown in fig. 4.3.1. to switch cpu and dma buses, an external circuit is required. an example for the connection of this ic to an scsi control ic where cpu and dma buses are separated (ex. cxd1185aq) is shown in fig. 4.3.2. 4.3.2 data transfer between scsi control ic and the buffer memory data transfer between scsi control ic and buffer memory is performed through this ic. (1) data transfer handshake xhac/sdrq become the data transfer request signal sdrq from scsi control ic to this ic. hdrq/xsac become the corresponding acknowledge signal xsac. 1 data transfer from scsi control ic to this ic (hsrc at ?? when hdmaen is at ?? sdrq input while fifo is not full will make this ic activate xsac. data is written into fifo with the rising edge of xhwr. 2 data transfer from this ic to scsi control ic (hsrc at ?? when hdmaen is at ?? sdrq input while fifo is not empty will make this ic activate xsac. it also outputs data from fifo to hdb0 to 7 during the period xhac is at ??
sram cxd2500q cpu cxd1186cq/cr adpcm decoder adrq xaac data bclk lrck c2po xmwr xmde ba0?5 bdb0?,p xwr xrd xcs a0? db0? int 80 type host bus hmds = ? xhin hdrq xhac xhwr xhrd xhcs ha0, 1 hdb0-7, p fig. 4.1 cxd1186cq/cr connection (80 type host bus) ?0 cxd1186cq/cr (2) completion of data transfer the 2 following methods are for the completion of data transfer. hxfrc is used. hdmaen is set to ?? for either method refer to paragraph 4.2.2. (3) data transfer cycle the data transfer cycle between this ic and scsi control ic can be controlled through sdmacyc 0 and 1 bits from config register. cpu sets these bits in coordination with the speed of scsi control ic (see a.c characteristics) sdmacyc1 0 ? ? 3 cycles. ? ? 4 cycles. ? ? 5 cycles. (4) cpu control of the ic for cpu control of the ic when data transfer is executed between scsi control ic and the buffer memory, see paragraph 4.2.2.
?1 cxd1186cq/cr start rd status busy status? wr parameter wr command dma start rd status interrupt status rd result end interrupt processing rd intsts hstcmd = ??? rd hstcmd rd hstprm wr intclr 08 command start return command complete wr drv rslt wr hifctl y y y y n n n n fig. 4.2.1 host and cpu control
?2 cxd1186cq/cr starat n = n rd status n : number of transter byte dreqsts =??? rd rddata (wr wrdata) n = n ?1 n = 0 ? end n y fig. 4.2.2 i/o mode data transfer
?3 cxd1186cq/cr sram cxd2500q cxd1186cq/cr cxd1180aq cpu external circuit (for example g/a) data bclk lrck c2po xmwr xmde ba0?5 bdb0?, p xhac hdrq xhwr xhrd hdbp hdb0? address xrd xwr a0? db0? int xcs chip setect hmds = ? fig. 4.3.1 cxd1186cq/cr connection (connecting method 1 with scsi control ic) sram cpu cxd2500q data bclk lrck c2po xmwr xmde ba0?5 bdb0?, p xhac hdrq xhwr xhrd hdbp hdb0? xrd xwr a0? db0? int xcs cxd1186cq/cr hmds = ? cxd1185aq drq dack wed red d0-7 re we a0-3 c0-7 cs irq fig. 4.3.2 cxd1186cq/cr connection (connecting method 2 with scsi control ic)
?4 cxd1186cq/cr 5. data transfer between audio processor (adp) and buffer memory data transfer between adp and the buffer memory is performed through this ic. (1) data transfer handshake adrq pin is the data transfer request signal from adp to this ic. xaac pin becomes the corresponding acknowledge signal. when admaen is at ??and adrq is input while fifo is not empty, this ic activates xaac and outputs fifo data to hdb0 to 7 during the period where xaac is at ?? (note 1) hadrc and hxfrc are used for the transfer of data between both this ic and the host and this ic and adp. accordingly, hdmaen and admaen cannot be set to ??simultaneously. if both of then are set to ??simultaneously, hdmaen will turn to ??and admaen to ?? inside the ic. (note 2) even when hmds is at ??(connected to intel 80 type host bus), turning admaen to ??will make xhwr and xhrd pins change from input to output. therefore access from the host to this ic register is not possible. watch out for signals collision. (2) completion of data transfer there are 2 ways to complete data transfer. using hxfrc. turning admaen bit to ?? for details on the 2 ways refer to paragraph 4.2.2. (3) data transfer cycle the data transfer cycle between this ic and adp can be controlled using bits sdmacyc 0 and 1 from config register. cpu sets these bits to match adp transfer speed. sdmacyc 1 0 ? ? 3 cycles. ? ? 4 cycles. ? ? 5 cycles. (4) cpu control of the ic for cpu control of the ic when data is transferred between adp and the buffer memory, refer to paragraph 4.2.2. 6. cpu port dma cpu control of the ic an example on cpu control of the ic when cpu port performs dma is indicated in fig. 6.1 and fig. 6.2. when cpu port performs dam, the address uses dadrc. accordingly, when the decoder is performing any of the following modes write only, real time correction, cd-da, cpu cannot access the buffer memory. when csrc is at ?? turning cdmaen to ??(dmactl register) will cause data from the buffer memory to be read and written into cpubrdt register. when cdmaen is turned to ?? it is prohibited to change csrc value. to change csrc value turn cdmaen to ??
?5 cxd1186cq/cr n = n m = m set dadrc = m wr dmactl cdmaen = ? csrc = ? rd dmasts cbfbwrdy ? n = 0 ? n n y y wr cpubwpo wr cpubwdt n = n ?1 wr dmactl cdmaen = "l" end 1 2 3 4 5 6 7 8 n = 0 ? n = n m = m set dadrc = m wr dmactl cdmaen = ? csrc = ? rd dmasts cbfbwrdy ? n = 1 ? n y n y y y n = n ?1 end rd cpubrdt rd cbfrdpo wr dmactl cdmaen = ? 1 2 3 4 5 6 7 8 9 fig. 6.1 cpu buffer write control fig. 6.2 cpu buffer read control
package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 ?0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 ?0.1 + 0.15 14.0 ?0.1 + 0.4 17.9 0.4 16.3 0.1 ?0.05 + 0.2 2.75 ?0.15 + 0.35 0.8 0.2 0.15 ?0.05 + 0.1 80pin qfp (plastic) m 0.12 0.15 0?to 10 detail a a package outline unit : mm cxd1186cq cxd1186cr cxd1186cq/cr ?6 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 alloy package structure 14.0 0.2 * 12.0 0.1 (0.22) 60 41 40 21 20 80 61 1 0.18 ?0.03 + 0.08 a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (13.0) 0.1 0.1 0.5 0.2 0?to 10 detail a 80pin lqfp (plastic) 0.5g lqfp-80p-l01 lqfp080-p-1212 0.1 note: dimension * ?does not include mold protrusion. 0.13 m 0.5

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